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LH1692
LH1692
DESCRIPTION
The LH1692 is a 300-output TFT-LCD gate driver IC.
300-output TFT-LCD Gate Driver IC
PIN CONNECTIONS
319-PIN TCP TOP VIEW
FEATURES
* Number of LCD drive outputs : 300 * LCD drive output sequence : Output shift direction can be selected OG1/OG300 or OG300/OG1 * Cascade connection : Max. 4 cascades (internal counting system) * Usable with both positive/negative power supplies * Output mode selection - Normal mode (1-pulse scanning) - Continuous 2-pulse mode (2-pulse scanning) - Jumping 2-pulse mode (2-pulse scanning) * LCD drive voltage : +16.0 to +42.0 V * Operating temperature : -30 to + 85 C * Package : 319-pin TCP (Tape Carrier Package)
VDD VEE VSS VCC VLS TEST1 TEST2 CKV SPV CE1 CE2 R/L MODE1 MODE2 VLS VCC VSS VEE VDD 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301
1 OG1 2 OG2 3 OG3
CHIP SURFACE
298 OG298 299 OG299 300 OG300
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH1692
PIN DESCRIPTION
PIN NO. 1 to 300 301, 309 302, 318 303, 317 304, 316 305, 315 306, 307 308 309, 310 311 312 313, 314 SYMBOL OG1-OG300 VDD VEE VSS VCC VLS MODE2, MODE1 R/L CE2, CE1 SPV CKV TEST2, TEST1 I/O O - - - - - I I I I I I DESCRIPTION LCD drive output pins Power supply pins for LCD drive Power supply pins for LCD drive Power supply pins for logic system Power supply pins for logic system Power supply pins for input level shifter Output mode selection pins Pin for selecting bi-directional shift register and setting cascade sequence Cascade sequence setting pins Vertical scanning start pulse input pin Vertical shift clock input pin IC test pins
BLOCK DIAGRAM
MODE2 306 MODE1 307 R/L 308 CE2 309 CE1 310 SPV 311 CKV 312 TEST2 313 OUTPUT CIRCUIT TEST1 314 1 300 CONTROL LOGIC 1 LEVEL SHIFTER 300 1 BI-DIRECTIONAL SHIFT REGISTER 300
301 319 305 315 304 316 302 318 303 317 VDD VDD VLS VLS VCC VCC VEE VEE VSS VSS
1 OG1
300 OG300
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LH1692
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Control Logic Bi-directional Shift Register Level Shifter Output Circuit FUNCTION Used to create signals necessary for mode selecting signal, cascade sequence setting signal and for operation of bi-directional shift register. Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive output sequence of OG1/OG300 direction or OG300/OG1 direction. Used as circuit which shifts LCD drive output signals transferred by bi-directional shift register to VDD-VEE level. Configured with output buffers to output VDD-VEE level.
INPUT/OUTPUT CIRCUITS
VLS
I
VSS
,
To Internal Circuit
Level Shifter Internal Logic (VLS-0 V/VCC-VSS) (VCC-VSS)
Applicable pins SPV, CKV, CE1, CE2, R/L, MODE1, MODE2, TEST1, TEST2
Fig. 1 Input Circuit
VDD
O
From Internal Circuit (VDD-VEE)
VEE
Applicable pins OG1-OG300
Fig. 2 Output Circuit
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LH1692
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VDD VLS VCC VEE VSS CKV SPV FUNCTION Used as power supply pin for high level LCD drive. Used as power supply pin for input level shifters. Used as power supply pin for logic system, normally connected to VSS + 5.0 V. Used as power supply pin for low level LCD drive. Used as logic system power supply pin. Used as vertical shift clock pulse input pin. Used as vertical scanning start pulse input pin. (At least, input one cycle of CKV during "L" period of SPV.) Used as input pins for selecting output mode. Output mode is set as shown in the table below by setting MODE1 pin and MODE2 pin. MODE1 MODE1 MODE2 H L H L MODE2 H H L L Output mode Normal mode (1-pulse scanning) Continuous 2-pulse mode Jumping 2-pulse mode Set all outputs to VEE level.
Used as input pin for selecting the shift direction of bi-directional shift register and for setting the sequence of cascade connection. R/L LCD drive outputs shift from OG1 to OG300 when set to "H". LCD drive outputs shift from OG300 to OG1 when set to "L". At the same time, cascade sequence is set as shown in the table below. Used as input pins for setting of chip cascade sequence. (Max. 4 cascades) Cascade sequence CE2 CE1 R/L = "H" R/L = "L" CE1 CE2 H L H L TEST1 TEST2 OG1-OG300 H H L L 1st 2nd 3rd 4th 4th 3rd 2nd 1st
With above setting, sets the cascade sequence signal inside the IC. Used as input pins for IC testing. Must be set to "H". Used as output pins for LCD drive output, and which output data at 2 levels. * Selecting data is output at VDD level . * Non-selecting data is output at VEE level .
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LH1692
Functional Operations
(1) Example of Cascade Sequence (One Side Assembled)
OG1 CE1 = "H" CE2 = "H" OG300 OG1 CE1 = "L" CE2 = "H" OG300 TFT-LCD Panel OG1 CE1 = "H" CE2 = "L" OG300 OG1 CE1 = "L" CE2 = "L" OG300 Scanning Direction When R/L = "L". Scanning Direction When R/L = "H".
* At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H", jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L", continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and output VEE level is set when MODE1 = "L" and MODE2 = "L".
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LH1692
(2) Example of Input/Output Timing (For 1st Cascade Sequence)
CKV SPV
OG1 OG2 OG3 OG1 OG2 OG3
OG300 OG299 OG298 OG300 OG299 OG298
(1-pulse Mode)
(Jumping 2-pulse Mode)
R/L = "H" R/L = "L"
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LH1692
(3) Example of Cascade Sequence (Both Side Assembled)
OG1 CE1 = "H" CE2 = "H" OG300 OG300 CE1 = "H" CE2 = "L" OG1 TFT-LCD Panel OG1 CE1 = "L" CE2 = "H" OG300 OG1 OG300 CE1 = "L" CE2 = "L"
Scanning Direction When R/L = "L". Scanning Direction When R/L = "H".
* At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H", jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L", continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and output VEE level is set when MODE1 = "L" and MODE2 = "L".
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LH1692
(4) Example of Input/Output Timing (For 1st Cascade Sequence)
CKV SPV
OG1 OG2 OG3 OG1 OG2 OG3
OG300 OG299 OG298 OG300 OG299 OG298
(1-pulse Mode)
(Continuous 2-pulse Mode)
R/L = "H" R/L = "L"
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LH1692
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. Logic system power supply (VLS) or internal logic system power supply (VSS, VCC; VCC > VSS) / logic input / LCD drive power supply (VEE, VDD) It is possible to set voltage VEE to the same as VSS. When connecting the power supply when VEE = VSS, observe the following sequence and the recommended sequence figure shown below. Logic system power supply (VLS), internal logic system power supply (VSS, VCC; VCC > VSS) and low-level LCD drive power supply (VEE) / logic input / high-level LCD drive power supply (VDD) When disconnecting the power supply, follow the reverse sequence. Since the logic state of the internal circuit is unstable immediately after the logic system power is supplied, input CKV and SPV while initializing the internal circuit (minimum input clock number is 300 CKV). MODE1 and MODE2 should be set to "L" during the initializing period for setting the LCD drive output to VEE level.
VDD VLS Input 0V
VCC VSS, VEE
Input pin setting Input pins other than CKV and SPV must be set to "H" or "L" level.
Maximum ratings When connecting or disconnecting the power, this IC must be used within the range of the absolute maximum ratings.
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LH1692
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VDD VLS Supply voltage VCC - VSS VEE - VSS VDD - VEE (VSS) Input voltage Storage temperature VIN TSTG APPLICABLE PINS VDD VLS VCC, VSS VEE, VSS VDD, VEE, VSS CKV, SPV, CE1, CE2, R/L, MODE1, MODE2, TEST1, TEST2 RATING -0.3 to +45.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to +45.0 -0.3 to +45.0 -0.3 to VLS + 0.3 -45 to +125 UNIT V V V V V V C 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to 0 V.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL VDD VLS VEE - VSS VDD - VEE (VSS) VIN TOPR MIN. +5.5 +3.0 0 +16.0 0 -30 +25.0 TYP. +9.0 +5.0 +5.0 MAX. +42.0 +5.5 +5.5 +11.0 +42.0 VLS +85 UNIT V V V V V V C 1, 2 NOTE
Supply voltage
VCC - VSS +3.0
Input voltage Operating temperature
NOTES :
1. The applicable voltage on any pin with respect to 0 V. 2. Ensure that voltages are set as follows. VSS, VEE 0 V VCC - VSS = VLS0.1 V (For 3.3 V specifications) VCC - VSS = VLS0.2 V (For 5.0 V specifications) VCC VLS
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LH1692
When power supply pins are set as shown below, the LH1692 can output positive voltage and negative voltage to LCD drive output. Example 1 : For Positive Voltage Output
VDD LCD Drive Output
VLS, VCC VSS, VEE (0 V)
Input
Internal Logic
Example 2 : For Negative Voltage Output
VDD, VLS 0V Input LCD Drive Output
VCC VSS, VEE
Internal Logic
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LH1692
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "Low" current Input "High" current
(VLS = +3.30.3 V (= VCC - VSS), VEE = VSS, TOPR = -30 to +85 C)
APPLICABLE PINS CKV, SPV, MODE1, MIN. TYP. MAX. 0.2VLS VEE + 0.4 VDD - 0.4 5.0 5.0 60 130 80 50 130 For jumping 2-pulse mode 200 90 50 130 For continuous 2-pulse mode 200 90 90 UNIT V V V V A A A A A A A A A A A A A A 4 3 1 NOTE
SYMBOL CONDITIONS VIL VIH VOL VOH IIL IIH IDD ILS ICC IEE IDD ILS ICC IEE IDD ILS ICC IEE IOL = 0.4 mA IOH = -0.4 mA VI = 0 V VI = VLS For 1-pulse mode
MODE2, CE1, CE2, R/L 0.8VLS OG1-OG300 CKV, SPV, MODE1, MODE2, CE1, CE2, R/L
Supply current (1)
2
Supply current (2)
Supply current (3)
NOTES :
1. All input pins : 3.3 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz Other input pins : 3.3 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 3.3 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 3.3 V All output pins are opened.
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LH1692
(VLS = +5.00.5 V (= VCC - VSS), VEE = VSS, TOPR = -30 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "Low" current Input "High" current SYMBOL CONDITIONS VIL VIH VOL VOH IIL IIH IDD Supply current (1) ILS ICC IEE IDD Supply current (2) ILS ICC IEE IDD Supply current (3) ILS ICC IEE For continuous 2-pulse mode For jumping 2-pulse mode For 1-pulse mode IOL = 0.4 mA IOH = -0.4 mA VI = 0 V VI = VLS APPLICABLE PINS CKV, SPV, MODE1, MIN. TYP. MAX. 0.2VLS VEE + 0.4 VDD - 0.4 5.0 5.0 60 180 100 50 130 300 150 50 130 300 150 50 UNIT V V V V A A A A A A A A A A A A A A 4 3 1 NOTE
MODE2, CE1, CE2, R/L 0.8VLS OG1-OG300 CKV, SPV, MODE1, MODE2, CE1, CE2, R/L
2
NOTES :
1. All input pins : 5 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz Other input pins : 5 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 5 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 s SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 5 V All output pins are opened.
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LH1692
AC Characteristics
PARAMETER Clock frequency "L" clock pulse width Clock rise time Clock fall time Data setup time Data hold time Pulse rise time Pulse fall time Output transfer delay time Output rise time Output fall time
(VLS = +3.30.3 V (= VCC - VSS), VEE = VSS, TOPR = -30 to +85 C)
APPLICABLE PINS MIN. 0.5 100 100 CKV, SPV SPV 100 300 100 100 3.0 CL = 500 pF OG1-OG300 1.0 1.0 TYP. MAX. 100 UNIT kHz s ns ns ns ns ns ns s s s
SYMBOL CONDITIONS fCKV tWL tRCKV tFCKV tSU tH tRSPV tFSPV tD tR tF
CKV
(VLS = +5.00.5 V (= VCC - VSS), VEE = VSS, TOPR = -30 to +85 C)
PARAMETER SYMBOL CONDITIONS Clock frequency fCKV "L" clock pulse width tWL Clock rise time Clock fall time Data setup time Data hold time Pulse rise time Pulse fall time Output transfer delay time Output rise time Output fall time tRCKV tFCKV tSU tH tRSPV tFSPV tD tR tF CL = 500 pF OG1-OG300 CKV, SPV SPV 100 300 100 100 2.0 1.0 1.0 APPLICABLE PINS MIN. 0.5 100 100 TYP. MAX. 100 UNIT kHz s ns ns ns ns ns ns s s s
CKV
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LH1692
Timing Chart
tFCKV CKV 90% 10% tSU tFSPV SPV 90% 10% tWL tRCKV 90% 10% tH tRSPV 90% 10% tD 90% 50% OG1-OG300 (1-pules Mode) tD 10% tR tD tD 90% 50% 10% tF 50% 50% 50% 50% 50% 50%
50% OG1-OG300 (Continuous 2-pulse Mode)
50%
tD
tD
50% OG1-OG300 (Jumping 2-pulse Mode)
50%
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PACKAGE
LH1692F
TEST2
TEST1
MODE2
MODE1
26.750.7(Good device hole) 36.00.06 31.0 (SL) P1.2 x (25 - 1) = 28.80.06 W0.400.02 0.40.02 O1.9 (PI) 2-O1.5 (Cu hole) O2.0 (Good device hole) 2-O2.7 (Cu)
COM1 VCC VDD VSS VEE CE1 VLS COM1 R/L VDD CKV VEE VSS 63.9490.12 Film center Device center SPV CE2 VLS VCC COM2
COM3
COM4
COM4
5.00.7 (Good device hole)
5.0 (SL)
UPILEX is a trademark of UBE INDUSTRIES, LTD..
Sprocket center 5.3MAX. (Resin area) Chip center 20.4MAX. (Resin area)
2.7 (SR) 2.0 (SL) 3.0 (SL)
[5.5 (E.L.)]
10.0 (SL)
5.0 (SL)
6.5 (SR) 8.50.05
[10.0 (E.L.)] [15.5 (E.L.)]
16
P0.14 x (308 - 1) = 42.980.085 W0.070.02 22.1 (SR) 44.60.085 (Mark) 1.0 (SL) 22.7 (SL) [46.0 (E.L.)] OG238 OG239 OG300 DUMMY COM2 COM1 COM1 22.7 (SL) 22.1 (SR)
1.9810.05 0.3MAX. Pattern side 1.0 (SL) 0.75MAX. Backside COM4 COM4 COM3 DUMMY OG1 OG2 OG3 1.2MAX. Total
1.9810.05
4.750.05
[3.5TYP. (3.2MIN.)]
PACKAGES FOR LCD DRIVERS
0.60.02
0.40.02
0.40.02 0.60.02
o Tape Specification
Tape width Tape type Perforation pitch 70 mm Wide 4 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 USLP 18 m Epoxy resin (Unit : mm)

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